1. Field of the Invention
This invention relates to a semiconductor circuit and more particularly to a semiconductor integrated circuit on which an electrostatic discharge (ESD) protection circuit for use in preventing damage to an internal circuit caused by an ESD and application of surges is installed.
2. Description of Related Art
On the semiconductor integrated circuit is installed an ESD protection circuit for use in protecting an internal circuit against a surge applied to input/output pads. One of the well-known circuit topologies in the ESD protection circuit is a circuit topology using a silicon controlled rectifier (SCR). The ESD protection circuit using the SCR has an advantage that a discharging capability for performing an active operation is high when the surge is inputted, and this circuit is thus widely used.
The ESD protection circuit using the SCR is typically constituted by a SCR and a trigger element connected to the gate of the SCR. One of the elements to be used as the trigger element is a PMOS transistor. For example, Japanese Patent Laid-Open Application No. 2003-318265 discloses an ESD protection circuit having a configuration in which the PMOS transistor is connected to the gate of P gate-type SCR (refer to FIG. 1). The ESD protection circuit in FIG. 1 is constituted by the SCR and the PMOS transistor 105. Anode of the SCR is connected to an I/O pad 102, and its cathode is connected to VSS pad 103. The gate of the SCR is connected to a drain of the PMOS transistor 105. The gate of the PMOS transistor 105 is connected to a VDD pad 101, and its source and backgate are connected to the I/O pad 102. Further, although FIG. 2 of Japanese Patent Laid-Open Application No. 2003-318265 illustrates the ESD protection circuit where the input circuit 104 is connected to the VDD pad 101, this illustration would be an erroneous expression.
In addition, as the trigger element, the NMOS transistor may also be used. Japanese Patent Laid-Open Application No. 2003-203985 and its corresponding U.S. Patent Application, i.e. U.S. Pat. No. 6,545,321 disclose an ESD protection circuit having a configuration in which the NMOS transistor acting as a trigger element is connected to the gate of N-gate type SCR. In addition, Japanese Patent Laid-Open Application No. 2006-303110 discloses a configuration in which the PMOS transistor is used as the trigger element and also the NMOS transistor is used.
In addition, as already been disclosed in the reference: M. Mergens et al., IEEE rans. Device Materi. Reliab. vol. 5, no. 3, pp. 532-542, September 2005, it is also possible to use diodes connected in series as the trigger element. FIG. 2 shows a configuration of the ESD protection circuit having such a configuration as above. The ESD protection circuit shown in FIG. 2 is constituted by the SCR and the diodes 106 connected in series. Anode of the SCR is connected to the I/O pad 102 and its cathode is connected to the VSS pad 103. As the trigger element, the diodes 106 connected in series in a forward direction from the gate of the SCR toward the VSS pad 103 are used.
One requirement applied to the ESD protection circuit consists in the fact that a leakage current at the I/O pad is low during normal operation. That is, under a condition in which the VDD pad is kept at the power supply voltage level VDD and the VSS pad is kept at the ground level VSS, it is preferable that the leakage current flowed from the I/O pad through the ESD protection circuit is low. The leakage current in the I/O pad is important in reduction of a consumption current in the semiconductor integrated circuit.
Another requirement applied to the ESD protection circuit consists in a low trigger voltage in which the SCR starts to operate during ESD stress condition, in particular, a low trigger voltage when an ESD stress of positive voltage for the VSS pad is applied to the I/O pad. A circuit topology using the SCR shows a tendency that the trigger voltage becomes high when the ESD stress of positive voltage for the VSS pad is applied to the I/O pad, in particular. If the trigger voltage is high, it shows a certain problem because an internal circuit may be damaged.
However, the aforementioned ESD protection circuit cannot satisfy these both requirements. For example, although the ESD protection circuit shown in FIG. 1 can reduce the trigger voltage of the SCR, it cannot reduce the leakage current of the I/O pad. A reason why this occurs consists in the fact that a value of leakage current in the I/O pad 102 when “High” level (i.e. a power supply voltage level VDD) is applied to the I/O pad 102 is determined by an off-leakage current IOFF of the PMOS transistor 105. In this case, the off-leakage current IOFF is a drain-source current IDS when both a gate-source voltage VGS and a backgate-source voltage VBS of the PMOS transistor 105 are 0V. With such a configuration as described above, the leakage current at the I/O pad 102 cannot be reduced to a value less than the off-leakage current IOFF of the PMOS transistor 105.
Even the ESD protection circuit in FIG. 2 can reduce the trigger voltage of the SCR by reducing the number of the diodes 106. However, the leakage current at the I/O pad 102 is high because the diodes 106 are connected in a forward direction toward the ground line (the power source line connected to the VSS pad 103).
B. Keppens et al., EOS/ESD Symposium Proceedings, 4B.7, 2004 disclose the ESD protection circuit for satisfying aforementioned both two requirements. FIG. 3A shows a circuit diagram indicating a configuration of the ESD protection circuit disclosed in this document. The ESD protection circuit in FIG. 3A is provided with N-gate type SCR. The anode of the SCR is connected to the I/O pad 102 and its cathode is connected to the VSS pad 103. A gate G2 of the SCR is connected to the VDD pad 101 through a resistor R2.
FIG. 3B is a view for showing a sectional structure of the semiconductor integrated circuit for realizing the ESD protection circuit shown in FIG. 3A. The ESD protection circuit shown in FIG. 3A is integrated at the P-type substrate 111 having N-well 112 formed the rein. The P-type substrate 111 is formed with P+ region 113 and N+ region 114, and the P+ region 113 and N+ region 114 are connected to the VSS pad 103. In this case, P+ region is a region where P-type impurities are doped under a high concentration and N+ region is a region where N-type impurities are doped under a high concentration. In addition, an N-well region 112 is formed with a P+ region 115 and an N+ region 116. The P+ region 115 is connected to the I/O pad 102 and the N+ region 116 is connected to the VDD pad 101. The P+ region 115, N-well 112, P-type substrate 111 and N+ region 114 act as a SCR (having PNPN structure). The P+ region 113, N+ region 114, P+ region 115, and N+ region 116 are separated from each other by field oxide films 117. The resistor of the P-type substrate 111 acts as a resistor element R1 in FIG. 3A and a resistor of the N-well 112 acts as a resistor element R2.
A leakage current at the I/O pad 102 is less in the ESD protection circuit of FIG. 3A because the gate G2 of the SCR is clamped at the power source voltage level VDD during its normal operation. In addition, when the ESD stress of positive voltage is applied to the I/O pad against the VSS pad 103, the VDD pad 101 is of a floating condition, so that a forward biasing may easily be applied between the anode and gate G2 of the SCR. Accordingly, the ESD protection circuit in FIG. 3A can reduce the trigger voltage of the SCR.
However, the ESD protection circuit in FIG. 3A shows a problem that a pn junction between the P+ region 115 and N-well 112 may easily be damaged when an ESD stress of negative polarity for the VDD pad 101 is applied against the I/O pad 102. This problem is particularly serious when an area of the pn junction between the P+ region 115 and N-well 112 is reduced so as to reduce a parasitic capacitance of the SCR. Accordingly, the ESD protection circuit in FIG. 3A cannot be a practical one.
As described above, it is believed that it has not been well known in the art that such a practical technology as one satisfying the two requirements of reduction of the leakage current at the I/O pad under the normal operating state and reduction of trigger voltage when the ESD stress of positive voltage is applied to the I/O pad with respect to the VSS pad.